1. Field of the Invention
The present invention relates to a processing pulse control circuit for use in devices performing signature analysis of digital circuits.
2. Description of the Prior Art
Parallel with the recent exponential growth in the use of Large Scale Integrated (LSI) digital circuits has come the development of a number of different approaches directed toward testing for the correct operation of these digital circuits. U.S. Pat. No. 4,441,074, issued to Bockett-Pugh et al, discloses a digital circuit tester for performing signature analysis, whereby faults in the signature analysis can be exactly located and recorded for subsequent inspection. U.S. Pat. No. 4,510,572, issued to Reece et al, discloses an entire complex digital system analyzer wherein the data signature at different nodes in a device under test can be tested. Other examples of different prior art approaches include: U.S. Pat. No. 4,513,418 issued to Bardell, Jr.; U.S. Pat. No. 4,534,028 issued to Trischler; and U.S. Pat. No. 4,357,703 issued to Van Brunt.
The general test approach to which the present invention is directed is that of signature analysis of a device in response to a digital test pattern. A description of a simplified form of such a signature analysis system follows.
In the simplified signature analysis approach shown in FIG. 1A, a clock pulse is applied along lines 10 to a test pattern generator 20. A graph of the clock pulses applied to the device along lines 10 is shown in FIG. 1D. The test pattern generator 20 outputs a digital test pattern to be inputted to a device under test (DUT), to facilitate signature analysis of that device. The test pattern is outputted along lines 30, 31, 32. . . 30+N, and is in the form of binary logic values (i.e. 1's and 0's). The number of bits in the test pattern outputted per clock pulse corresponds to the number of bits processed by the device under test. Every time a clock pulse is received along lines 10, a test pattern increment is outputted as indicated in FIG. 1B. The overall sequence of these test pattern increments corresponds to the test pattern.
The test pattern increments outputted along the lines 30, 31, 32, . . . 30+N are fed to the inputs of a device under test (DUT) 40. The clock pulses are also fed to the device under test 40 along lines 10. Upon receipt of the next clock pulse along lines 10, the device under test 40 inputs the test pattern increment available at its inputs. The test pattern increment is then processed by the device under test 40 in synchronization with the clock pulses received along lines 10, and a signature pattern increment is generated in response thereto. The signature pattern increment outputted along the signature pattern bit lines 50, 51, 52. . . 50+N is also of the form of logical 1's and 0's as indicated in FIG. 1C. The number of bits in a signature pattern increment is unique to each type of device 40, and may vary from one bit to eight bits, or more.
Several aspects should be noted about FIG. 1C. First, the clock pulse counts D, D+1, D+2, etc. in FIG. 1C correspond to the clock pulse counts 1, 2, 3, etc. in FIG. 1B. D is the delay time which corresponds to the number of clock pulses required for the first signature pattern increment to emerge from the device under test 40. This delay occurs because it takes several clock pulses for the test pattern increment to be inputted to the device under test 40, and then it may take several more clock pulses for the device under test 40 to process the test pattern increment and output the signature pattern increment.
The signature pattern increments outputted by the device 40 along signature pattern bit lines 50, 51, 52 . . . 50+N are fed to the inputs of a signature recording device 60 which also has a clock input fed by lines 10. In this prior art device shown in FIG. 1A, the recording pulses applied to the signature recording device 60 correspond to the clock pulses applied to the device 40 along lines 10. There is a one-to-one correspondence between the clock pulses shown in FIG. 1D and the recording pulses shown in FIG. 1E. Upon receipt of each clock pulse along lines 10, the signature recording device 60 records all signature pattern increments available at its inputs. The signature recording device 60 may be of a Multiple Input Shift Register (MISR) type construction, or any other suitable construction which facilitates the recording of the signature pattern increments.
Once recorded in the signature recording device 60, the entire signature pattern of the device under test 40 is compared to the signature pattern of a known good device. If the signatures are found to match, the device under test 40 is considered a good device. If the signatures differ, the device under test 40 is considered defective.
In the past, the digital test pattern was a unique series of digital inputs which was especially formulated to correspond to completely test a particular type of device. This approach has been found very expensive and time consuming in this age of Very Large Scale Integrated Circuits (VLSIC), because the digital test pattern for a VLSIC often encompasses a series of millions of digital inputs which must be formulated and, then, supplied to the testing site to be input to the test pattern generator 20.
As a result, there has been a trend in the semiconductor testing industry toward conducting Random Pattern Testing (RPT) of VLSIC devices. In this approach, a pseudo-random digital pattern is used as a test pattern in testing VLSIC devices. The testing pattern is described as pseudo-random because the pattern used is actually known, and is permanently stored in the testing equipment to be generically applied in the testing of all types of VLSIC devices.
Although the RPT testing approach is advantageous in that a unique testing pattern need not be formulated and input for each type of device to be tested, there is a tradeoff with corresponding disadvantages. The major disadvantage is that the pseudo-random test pattern may not be an ideal testing pattern to test a particular type of VLSIC device. One result which often occurs is that many signature pattern increments may be worthless for signature analysis because they represent "indeterminate" signature increments. An "indeterminate" signature increment, as opposed to a "determinate" signature increment, will now be further explained with reference to FIG. 1C.
A signature pattern increment of a device under test 40 is "determinate" when the output signature pattern increment for a given test pattern increment would be stable if repeatedly tested. In FIG. 1C, for example, clock pulse counts D, D+2 and D+3 all have normal determinate signature pattern increments, and are represented by 1's and 0's along the signature pattern bit lines 50, 51, 52 . . . 50+N.
In contrast, a signature pattern increment of a device under test 40 is "indeterminate" when the output signature pattern increment for a given test pattern increment would be unstable (i.e. unpredictable) if repeatedly tested. A term often used synonomously for "indeterminate signature pattern increment" is "X-state". FIG. 1C also includes indeterminate signature pattern bits (indicated by *'s) along the signature pattern bit lines 50, 51 and 51, 50+N for clock pulse counts D+1 and D+4, respectively. Thus, the signature pattern increments at clock pulse counts D+1 and D+4 represent counts where indeterminate signature pattern increments will occur.
The above described signature analysis system of FIG. 1A has been found disadvantageous in that indeterminate signature pattern increments, which are useless in signature comparison, are also recorded by the signature recording device 60. Therefore, such a signature analysis system is indeterminate in terms of device signature recording.
One prior art device which attempts to overcome this inefficiency is that disclosed by McMahon in U.S. Pat. No. 3,740,646, and it will be described with reference to FIG. 2A of the present application. Elements with functions matching those shown in FIG. 1A are given the same reference numerals. FIGS. 2B and 2C exactly correspond to FIGS. 1A and 1B.
Turning now to FIG. 2A, there is shown a signature analysis system which is similar to that in FIG. 1A, with additional elements being shown within the dashed area 70. A clock line 80 receives the clock pulses along lines 10 and applies these pulses to the count input of an increment counter 90. The clock pulses applied to the device 40 via lines 10 and to the increment counter via line 80 are shown in FIG. 2D which exactly corresponds to FIG. 1D.
Increment counter 90 produces a count which corresponds to the number of clock pulses which has been received along clock line 80. The count output from increment counter 90 is applied along lines 100 to the address inputs of a memory 110 to address a memory location corresponding to the count output. The contents at this memory location are outputted as 1's and 0's bits on lines 120, 121, 122 . . . 120+N. As will become clear in the discussion to follow, both the number of memory 110 output bits and the number of bit lines 120, 121, 122 . . . 120+N must exactly match the number of signature pattern bit lines 50, 51, 52 . . . 50+N.
The output bits on lines 120, 121, 122 . . . 120+N are applied to the control inputs of gates 130, 131, 132 . . . 130+N, respectively. Thus, the memory bits of 1's and 0's in the memory 110 are used to control the gating action of the gates 130, 131, 132 . . . 130+N.
Gates 130, 131, 132 . . . 130+N, in turn, receive as inputs the bits of the signature pattern increments on the signature pattern bit lines 50, 51, 52 . . . 50+N, respectively. If the appropriate control bit has been applied to a respective gate 130, 131, 132 . . . or 130+N, the bit of the signature pattern increment will be allowed to pass through the gate.
The chart of FIG. 2F shows examples of the gate outputs which are applied to parallel adder 140 along lines 150, 151, 152, . . . 150+N. Note that the symbol "-" indicates an indeterminate signature pattern bit which has not been allowed to pass through a gate 130, 131, 132, . . . or 130+N. An example is shown in FIG. 2F for the gate output line 150 at the clock pulse count D+1 (directly corresponding to the indeterminate signature pattern bit at line 50 and clock pulse count D+1 in FIG. 2C).
As shown in FIG. 2A, the parallel adder 140 adds the number of logical 1 bits received during a signature pattern increment, and this signature increment bit total is applied via lines 160 to the inputs of a signature recording device 60. As was the case for the device described with respect to FIG. 1A, the signature recording device 60 in FIG. 2A also receives recording pulses (FIG. 2E) which exactly correspond to the clock pulse applied via lines 10 (FIG. 2D). Upon receipt of a recording pulse, the signature recording device 60 records any signature increment bit total available at its input.
FIG. 2G is a chart showing examples of the recorded signature increment bit totals corresponding to the gate outputs shown in FIG. 2F. Note that indeterminate signature pattern bits are effectively blocked from being received by the parallel adder 140, and are therefore ignored in arriving at the recorded signature increment bit totals. Thus, the way in which this prior art device addresses the indeterminate signature pattern problem is to use the gates 130, 131, 132 . . . 130+N to prevent any indeterminate signature pattern bits from reaching the parallel adder 140 and, thus, from being included in the increment total.
Although this approach addresses the indeterminate signature increment problem to avoid faulty signature recording, it also has been found disadvantageous in that the treating of individual indeterminate signature bits requires complicated construction and programming. In regard to the programming, note that a control pattern increment must be provided to control the gating action of the gates 130, 131, 131, . . . 130+N for each signature pattern increment. This is expensive and time consuming, because a control pattern must be formulated, possibly for millions of signature pattern increments, and then input into the gate control memory 110.
As a result of the complicated construction and programming, many signature analysis users have opted to ignore this approach and, instead, to utilize the cheaper, but still disadvantageous, approach which was described with reference to FIG. 1A. Consequently, there exists a need for an improved approach in dealing with indeterminate signature pattern increments in signature analysis testing of digital devices. More specifically, there exists a need for improvements which are neither complicated nor expensive in construction or programming.